1. Field of the Invention
The present invention relates to a field effect transistor structure and a method of manufacturing a MESFET (metal semiconductor field effect transistor), and more particularly to a field effect transistor which is high in breakdown voltage and is hence free from any gate lag.
2. Description of the Related Art
FIGS. 7(a) to 7(h) of the accompanying drawings show a conventional power field effect transistor (hereinafter also called FET) structure and its fabrication method. In this conventional fabrication method, firstly with a photoresist 6 as a mask, a gate recess 7 is formed in an n-GaAs (gallium, arsenic) layer 20 (FIG. 7(a)), and then a 7000-angstrom-thick SiO.sub.2 (silicon oxide) film 4 is deposited. Then, as a mask for dry etching, a WSi (tungsten silicide) film 8 is deposited by sputtering, and with a photoresist 9 as a mask over the WSi film 8, the WSi film 8 is etched by magnetron ion etching (MIE) and then the SiO.sub.2 film 4 is etched firstly by reactive ion etching (RIE) and, after the photoresist 9 has been removed, secondly by magnetron ion etching until the n-GaAs layer 20 is exposed (FIG. 7(b)). A gate metal (Wsi and TiNi/Pt/Au/Ti) 1 is deposited on the SiO.sub.2 film 4 by sputtering and evaporation (FIG. 7(c)) and is then shaped into an gate-electrode shape by ion milling (FIG. 7(d)). After the beneath-gate SiO.sub.2 film 4 is removed by vapor etching, a 1000-angstrom-thick SiO.sub.2 passivation film 5 is deposited by low pressure CVD (FIG. 7(e)), and ohmic metals (AuGeNi) 2, 3 and a silicon nitride(Si.sub.x N.sub.y) passivation film 10 are formed one after another (FIG. 7(f)). At that time, before formation of the SiO.sub.2 passivation film 5, the device is dipped in dilute hydrochloric acid for a short time to clean the semiconductor surfaces. As a substitute for dilute hydrochloric acid, oxygen plasma may be used for cleaning the semiconductor surface. Then a photoresist 11 is patterned for formation of electrodes, whereupon an electrode metal (Ti/Pt/Au) 12 serving also as a conductor path during plating gold is deposited by sputtering (FIG. 7(g)). Subsequently with the photoresist as a mask, a gold electrode 13 of an approximately 3 .mu.m thickness is formed by plating gold, and then with the gold electrode 13 as a mask, the unnecessary part of the electrode metal 12 is removed by ion milling. Thus fabrication of the field effect transistor has been completed (FIG. 7(h)).
In a power field effect transistor, a breakdown voltage between the gate and drain or a breakdown voltage between the source and drain is significant parameters for determining a maximum output power of the device. These breakdown voltages are known to be delicately dependent on the kind of the SiO.sub.2 passivation film 5 and its fabrication method or the method of cleaning the semiconductor surface before formation of the SiO.sub.2 passivation film in the example of FIGS. 7(a) to 7(h). According to the experiences, if a passivation film and a process such as to improve the breakdown voltage of the device are used, a phenomenon that the drain current responds late with respect to the gate voltage application tends to become remarkable. In other words, there is a contracting relationship between increase of breakdown voltage of the device and reduction of the gate lag; that is, it is difficult to satisfy both at the same time.